Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CDB dual D type flip-flop. Logic levels present at the J and K inputs along with internal self-steering control the state of each flipflop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input. Thermal Resistance. TABLE 1.

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The Flip-Flop could typically operate at a speed of 16MHz even at high voltages like 15V with a low noise margin of only 2. Note: Complete Technical Details can be found at the CD datasheet attached at the end of this page. Meaning it has two JK flip flops inside it and each can be used individually based on our application.

The term JK flip flop comes after its inventor Jack Kilby. The JK flip flops are considered to be the most efficient flip-flop and can be used for certain applications on its own. The flip-flops are also called as latching devices meaning it can remember one single bit of data and latch the output based on it, due to this property they are commonly used as shift registers, control registers, storage registers or where ever a small memory is required.

The JK flip flop is considered to be more suitable for practical application because of its truth table that is the output of the flip flop will be stable for all types of inputs.

So if you are looking for a IC for latching purpose or to act as a small programmable memory for you project then this IC might be the right choice for you. The below circuit shows a typical sample connection for the JK flip-flop.

Note that the input pins are pulled down to ground through a 1k resistor or less, this way we can avoid the pin in floating condition. That is the pin will held to ground when the button is not pressed and when the button is pressed the pin will be held to supply voltage. The reset button should be pulled up through a 1K resistor and when grounded will reset the flip-flop.

The clock signal for the JK flip-flop is responsible for changing the state of the output. The flip-flop will change its output only during the rising edge of the clock signal. The clock signal here is just a push button but can be type of pulse like a PWM signal. The output state of the flip flops can be determined form the truth table below.

Normally during regular operation of the IC the reset pin will be set high and the clock pulse of known frequency will be supplied to the clock pin, then the value o J and K will be varied based on the input signals and the respective output will be obtained on the Q and Q bar pins.

This region of operation in highlighted in red colour on the Truth table above. Subscribe to stay updated with industry's latest Electronics components and news. Component Datasheet. CD Datasheet. Tags JK Flip Flop. Get Our Weekly Newsletter! These pins must be provided with clock pulse for the flip flop.


National Semiconductor








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